The invention relates to a method for implementing time switching, and to a time switch.
In this connection, time switch refers to a device capable of connecting the contents of any time slot in a frame structure of an incoming signal, to any time slot in an outgoing frame structure. In addition to a time switch, this device can also be called a time slot interchanger.
The problem involved in the switching of time slots in a TDM (Time Division Multiplex) signal, comprising frame blocks of different sizes (which will be illustrated below), is how the storage capacity can be efficiently utilized, in other words, how to minimize the need for connection memory. This problem is encountered, for instance, in the switching of an STM-1 signal in an SDH (Synchronous Digital Hierarchy) network. In the following, the structure of this signal will be described in greater detail.
FIG. 1 illustrates the structure of an STM-N frame used in a SDH network, and FIG. 2 illustrates a single STM-1 frame. The STM-N frame comprises a matrix with 9 rows and N.times.270 columns so that there is one byte at the junction point between each row and a respective column. Rows 1-3 and rows 5-9 of the N.times.9 first columns comprise a section overhead SOH, and row 4 comprises an AU pointer. The rest of the frame structure is formed of a section having a length of N.times.261 columns and containing the payload section of the STM-N frame.
FIG. 2 illustrates a single STM-1 frame which is 270 bytes in length, as described above. The payload section comprises one or more administration units AU. In the example shown in the figure, the payload section consists of the administration unit AU-4, into which a virtual container VC-4 is inserted. (Alternatively, the STM-1 transfer frame may contain three AU-3 units, each containing a corresponding lower-level virtual container VC-3). The VC-4, in turn, consists of a path overhead POH located at the beginning of each row and having the length of one byte (9 bytes altogether), fixed stuff FS located at the following two columns, TU-3 pointers or a null pointer indicator NPI located at the following three columns, fixed stuff or VC-3 path overheads (VC-3 POH) located at the following three columns, and the actual payload section PL. The null pointer indicator NPI is used to separate the tributary unit groups TUG-3 comprising TU-3 units from the tributary unit groups TUG-3 comprising TU-2 units.
FIG. 3 shows how the STM-N frame can be formed of existing bit streams. These bit streams (1.5, 2, 6, 8, 34, 45 or 140 Mbit/s, shown on the right in the figure) are packed at the first stage into containers C specified by CCITT. At the second stage, overhead bytes containing control data are inserted into the containers, thus obtaining the above-described virtual container VC-11, VC-12, VC-2, VC-3 or VC-4 (the first suffix in the abbreviations represents the level of hierarchy and the second suffix represents the bit rate). This virtual container remains intact while it passes through the synchronous network up to its point of delivery. Depending on the level of hierarchy, the virtual containers are further formed either into so-called tributary units TU or into AU units (AU-3 and AU-4) already mentioned above by providing them with pointers. An AU unit can be mapped directly into an STM-1 frame, whereas the TU units have to be assembled through tributary unit Groups TUG and VC-3 and VC-4 units to form AU units which then can be mapped into an STM-1 frame. In FIG. 3, the mapping is indicated by a continuous thin line, the aligning with a broken line, and the multiplexing with a continuous thicker line.
As is to be seen from FIG. 3, the STM-1 frame may be assembled in a number of alternative ways, and the contents of the highest-level virtual container VC-4, for instance, may vary, depending on the level from which the assembly has been started and in which way the assembly has been performed. The STM-1 signal may thus contain, e.g., 3 TU-3 units or 21 TU-2 units or 63 TU-12 units (or an arbitrary combination of some of the above-mentioned units). As the higher-level unit contains several lower-level units, e.g. the VC-4 unit contains TU-12 units (there are 63 such units in a single VC-4 unit, cf. FIG. 3), the lower-level units are mapped into the higher-level frame by interleaving, so that the first bytes are first taken consecutively from each one of the lower-level units, then the second bytes, etc. Accordingly, when the VC-4 signal contains, e.g., the above-mentioned 63 TU-12 signals, these signals are located in the VC-4 frame as shown in FIG. 2, i.e. the first byte of the first TU-12 signal is located first, then the first byte of the second TU-12 signal, etc. After the first byte of the last signal, i.e. the 63rd TU-12 signal, the second byte of the first TU-12 signal follows, etc.
The following table shows the contents of the columns of the STM-1 frame as a summary, depending on whether the frame contains TU-12, TU-2 or TU-3 units..
4 ______________________________________ Column Number TU-12 TU-2 TU-3 ______________________________________ 1-9 SOH SOH SOH 10 VC-4 POH VC-4 POH VC-4 POH 11-12 fixed stuff fixed stuff fixed stuff 13-15 NPI NPI TU-3 pointers 16-18 fixed stuff fixed stuff VC-3 POH 19-81 1x63xTU-12 3x21xTU-2 21x3xTU-3 82-144 1x63xTU-12 3x21xTU-2 21x3xTU-3 145-207 1x63xTU-12 3x21xTU-2 21x3xTU-3 208-270 1x63xTU-12 3x21xTU-2 21x3xTU-3 ______________________________________
The SDH system is described more closely, e.g., in References [1] to [3] (the references are listed at the end of the specification).
On the basis of the above, the frame of the STM-1 signal can be illustrated with respect to the switching as shown in FIG. 4. It consists of blocks of two types: e.g. the first 18 bytes, consisting of section and path overheads, on each row form the first block 41, and the following 63 bytes on each row form the second block 42, of which there are four successive ones in a single STM-1 frame 4. The data contained in the columns of the first block are not cross-connected (except for columns 13 to 18 in the case of TU-3 signals), but they continue in the same time slots even in the outgoing frame.
As stated above, the problem encountered in the switching of a signal of the type described above, consisting of frame blocks of different sizes, is how the storage capacity can be efficiently utilized; in other words, how to minimize the need for connection memory.
The drawback of the known time switches is that they demand a lot of storage capacity. Moreover, the memory control requires a fairly great deal of logic, which makes the practical equipment complicated.